--- old/src/hotspot/cpu/x86/assembler_x86.cpp	2019-04-08 15:45:54.921696722 +0800
+++ new/src/hotspot/cpu/x86/assembler_x86.cpp	2019-04-08 15:45:54.653682974 +0800
@@ -3099,7 +3099,7 @@
     }
     return;
   }
-  if (UseAddressNop && VM_Version::is_amd()) {
+  if (UseAddressNop && (VM_Version::is_amd() || VM_Version::is_hygon())) {
     //
     // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
     //  1: 0x90
--- old/src/hotspot/cpu/x86/vm_version_ext_x86.cpp	2019-04-08 15:45:55.541728516 +0800
+++ new/src/hotspot/cpu/x86/vm_version_ext_x86.cpp	2019-04-08 15:45:55.277714978 +0800
@@ -340,6 +340,10 @@
     return !is_amd_Barcelona();
   }
 
+  if (is_hygon()) {
+    return true;
+  }
+
   return false;
 }
 
@@ -407,6 +411,10 @@
     }
     return _family_id_intel[cpu_family_id];
   }
+  if (is_hygon()) {
+    return _family_id_hygon[cpu_family_id];
+  }
+
   return "Unknown x86";
 }
 
@@ -423,6 +431,9 @@
   } else if (is_amd()) {
     cpu_type = "AMD";
     x64 = cpu_is_em64t() ? " AMD64" : "";
+  } else if (is_hygon()) {
+  	cpu_type = "HYGON";
+	x64 = cpu_is_em64t() ? " AMD64" : "";
   } else {
     cpu_type = "Unknown x86";
     x64 = cpu_is_em64t() ? " x86_64" : "";
@@ -732,6 +743,34 @@
   "Opteron/Athlon64",
   "Opteron QC/Phenom"  // Barcelona et.al.
 };
+const char* const VM_Version_Ext::_family_id_hygon[] = {
+  "",	//family 0
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "",
+  "HygonGenuine",	//family 24
+};
+
 // Partially from Intel 64 and IA-32 Architecture Software Developer's Manual,
 // September 2013, Vol 3C Table 35-1
 const char* const VM_Version_Ext::_model_id_pentium_pro[] = {
--- old/src/hotspot/cpu/x86/vm_version_ext_x86.hpp	2019-04-08 15:45:56.061755178 +0800
+++ new/src/hotspot/cpu/x86/vm_version_ext_x86.hpp	2019-04-08 15:45:55.793741437 +0800
@@ -37,6 +37,7 @@
 
   static const char* const _family_id_intel[];
   static const char* const _family_id_amd[];
+  static const char* const _family_id_hygon[];
   static const char* const _brand_id[];
   static const char* const _model_id_pentium_pro[];
 
--- old/src/hotspot/cpu/x86/vm_version_x86.cpp	2019-04-08 15:45:56.565781009 +0800
+++ new/src/hotspot/cpu/x86/vm_version_x86.cpp	2019-04-08 15:45:56.301767478 +0800
@@ -1165,7 +1165,7 @@
     }
   }
 
-  if( is_amd() ) { // AMD cpus specific settings
+  if( is_amd() || is_hygon() ) { // AMD cpus specific settings
     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
       // Use it on new AMD cpus starting from Opteron.
       UseAddressNop = true;
@@ -1239,8 +1239,8 @@
     }
 #endif // COMPILER2
 
-    // Some defaults for AMD family 17h
-    if ( cpu_family() == 0x17 ) {
+    // Some defaults for AMD family 17h || Hygon family 18h
+    if ( cpu_family() == 0x17 || cpu_family() == 0x18 ) {
       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
--- old/src/hotspot/cpu/x86/vm_version_x86.hpp	2019-04-08 15:45:57.097808271 +0800
+++ new/src/hotspot/cpu/x86/vm_version_x86.hpp	2019-04-08 15:45:56.829794539 +0800
@@ -495,13 +495,13 @@
       result |= CPU_CX8;
     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
       result |= CPU_CMOV;
-    if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
+    if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || ((is_amd() || is_hygon()) &&
         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
       result |= CPU_FXSR;
     // HT flag is set for multi-core processors also.
     if (threads_per_core() > 1)
       result |= CPU_HT;
-    if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
+    if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || ((is_amd() || is_hygon()) &&
         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
       result |= CPU_MMX;
     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
@@ -576,8 +576,8 @@
     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
       result |= CPU_FMA;
 
-    // AMD features.
-    if (is_amd()) {
+    // AMD|Hygon features.
+    if (is_amd() || is_hygon()) {
       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
         result |= CPU_3DNOW_PREFETCH;
@@ -711,6 +711,7 @@
   static int  cpu_family()        { return _cpu;}
   static bool is_P6()             { return cpu_family() >= 6; }
   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
+  static bool is_hygon()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
   static bool is_zx()             { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS  '
   static bool is_atom_family()    { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
@@ -734,7 +735,7 @@
       if (!supports_topology || result == 0) {
         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
       }
-    } else if (is_amd()) {
+    } else if (is_amd() || is_hygon()) {
       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
     } else if (is_zx()) {
       bool supports_topology = supports_processor_topology();
@@ -770,7 +771,7 @@
     intx result = 0;
     if (is_intel()) {
       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
-    } else if (is_amd()) {
+    } else if (is_amd() || is_hygon()) {
       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
     } else if (is_zx()) {
       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
@@ -857,7 +858,7 @@
 
   // AMD features
   static bool supports_3dnow_prefetch()    { return (_features & CPU_3DNOW_PREFETCH) != 0; }
-  static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
+  static bool supports_mmx_ext()  { return (is_amd()||is_hygon()) && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
   static bool supports_lzcnt()    { return (_features & CPU_LZCNT) != 0; }
   static bool supports_sse4a()    { return (_features & CPU_SSE4A) != 0; }
 
@@ -870,7 +871,7 @@
   }
   static bool supports_tscinv() {
     return supports_tscinv_bit() &&
-           ( (is_amd() && !is_amd_Barcelona()) ||
+           ( ((is_amd()||is_hygon()) && !is_amd_Barcelona()) ||
              is_intel_tsc_synched_at_init() );
   }
 
@@ -896,7 +897,7 @@
     // Core      - 256 / prefetchnta
     // It will be used only when AllocatePrefetchStyle > 0
 
-    if (is_amd()) { // AMD
+    if (is_amd() || is_hygon()) { // AMD
       if (supports_sse2()) {
         return 256; // Opteron
       } else {
